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W83194R-630A
166MHZ CLOCK FOR SIS CHIPSET 1. GENERAL DESCRIPTION
The W83194R-630A is a Clock Synthesizer for SiS 540/630 chipset. W83194R-630A provides all clocks required for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium, Pentium II and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194R-630A makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194R-630A provides I2C serial bus interface to program the registers to enable or disable each clock outputs and W83194R-630A provides the 0.5%, 0.75% center type and 0~0.5% down type spread spectrum to reduce EMI. The W83194R-630A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
* Supports PentiumTM, PentiumTM II, AMD and Cyrix CPUs with I2C. * 3 CPU clocks * 14 SDRAM clocks for 3 DIMMs * 7 PCI synchronous clocks. * Optional single or mixed supply: (All Vdd = 3.3V) or (Other s Vdd = 3.3V, VddLCPU=2.5V) * Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns * SDRAM frequency synchronous or asynchronous to CPU clocks * Smooth frequency switch with selections from 66 to 166mhz * I2C 2-Wire serial interface and I2C read back * 0.5%, 0.75%center type, 0~0.5% down type spread spectrum to reduce EMI * Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) * 48 MHz for USB * 24 MHz for super I/O * Packaged in 48-pin SSOP
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY 3. BLOCK DIAGRAM
PLL2
48MHz
O2
24_48MHz
Xin Xout
XTAL OSC PLL1
Spread Spectrum
2
REF(0:1)
STOP
CPU_STOP# 3
CPUCLK(0:2)
*FS(0:3) 4 *MODE SEL3.3_2.5#
LATCH
5
14 PCI clock Divder
SDRAM(0:13)
POR
STOP
PCICLK(0:6) 7
CPU_STOP# PCI_STOP# PD# *SDATA *SCLK
Control Logic Config. Reg.
PCI_STOP#
4. PIN CONFIGURATION
Vdd REF0X2/ *FS3 Vss Xin Xout VddP PCICLK_F/ *FS1 PCICLK1/ *FS2 PCICLK2/*MODE Vss PCICLK3 PCICLK4 PCICLK5 PCICLK6 VddP Vss SDRAM 0/CPU_STOP# SDRAM 1/PCI_STOP# VddSD SDRAM 2/PD# SDRAM 3 Vss *SDATA *SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1 VddLCPU CPUCLK_F CPUCLK0 Vss CPUCLK1 VddSD SDRAM12 SDRAM_F Vss SDRAM11 SDRAM 10 VddSD SDRAM 9 SDRAM 8 Vss SDRAM 7 SDRAM 6 VddSD SDRAM 5 SDRAM 4 VddSD 48MHz/*FS0 24_48MHz/SEL2.5_3.3#
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY 5. PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k pull-up
5.1 Crystal I/O
SYMBOL Xin Xout PIN 4 5 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL CPUCLK_F PIN 46 I/O OUT FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. VddLCPU is the supply voltage for these outputs. This pin will not be stopped by CPU_STOP# Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. VddLCPU is the supply voltage for these outputs. SDRAM clock outputs which have syn. or asyn. frequencies as CPU clocks. This pin will not be stopped by CPU_STOP# SDRAM clock outputs which have syn. or asyn. frequencies as CPU clocks. CPU_STOP# input pin when MODE=0. SDRAM clock outputs which have syn. or asyn. frequencies as CPU clocks. PCI_STOP# input pin when MODE=0. SDRAM clock outputs which have syn. or asyn. frequencies as CPU clocks. PD# input pin when MODE=0. SDRAM clock outputs which have syn. or asyn. frequencies as CPU clocks. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks.
CPUCLK [ 0:1 ]
45,43
OUT
SDRAM_F
40
OUT
SDRAM0/CPU_STOP#
17
I/O
SDRAM1/PCI_STOP#
18
I/O
SDRAM2/PD#
20
I/O
SDRAM[3:12]
PCICLK_F/ *FS1
21,28,29,31,32 ,34,35,37,38, 41 7
OUT
I/O
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY
PCICLK 1/ *FS2 8 I/O PCI free-running clock during normal operation. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. PCI clock during normal operation. Latched input for MODE at initial power up for input selection of CPU_STOP#, PCI_STOP# and PD#. When MODE=1, the above pins are SDRAM clock outputs. When MODE=0, the pins are inputs ACPI pins. PCI clock during normal operation. Low skew (< 250ps) PCI clock outputs.
PCICLK 2/ *MODE
9
I/O
PCICLK [ 3:6 ]
11,12,13,14
OUT
5.3 I2C Control Interface
SYMBOL *SDATA *SDCLK PIN 23 24 I/O I/O IN
2
FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL REF0X2 / *FS3 PIN 2 I/O I/O FUNCTION 3.3V, 14.318MHz reference clock output . Internal 250k pull-up. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 3.3V , 14.318MHz reference clock output. SEL2.5_3.3# controls the Vdd of CPU. If logic 0 at power on, VddLCPU=3.3V. If logic 1, VddLCPU=2.5 24MHz or 48MHz selected by I2C for Super I/O. Internal 250k pull-up. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz output for USB during normal operation.
REF1 24_48MHz/ SEL2.5_3.3# 48MHz / *FS0
48 25
I/O I/O
26
I/O
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY 5.5 Power Pins
SYMBOL Vdd VddLCPU VddP VddSD Vss PIN 1 47 FUNCTION
Power supply for REF crystal and core logic. Power supply for CPUCLK_F and CPUCLK[0:1], either 2.5V or 3.3V. 6,15 Power supply for PCI outputs. 19,27,30,36,42 Power supply for SDRAM and 48/24NHz outputs. 3,10,16,22,33,39,44 Circuit Ground.
6. FREQUENCY SELECTION BY HARDWARE
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.8 100.2 83.3 133.6 75 100.2 100.2 133.6 66.8 97 97 95.2 140 112 96.2 166 SDRAM (MHz) 100.2 100.2 83.3 100.2 75 133.6 150.3 133.6 66.8 97 129.3 95.2 140 112 96.2 166 PCI (MHz) 33.4 33.4 33.2 33.4 37.5 33.4 33.4 33.4 33.4 32.3 32.3 31.7 35 37.3 32.1 33.3 REF (MHz) IOAPIC 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
7. SEL3.3_2.5# BUFFER SELECTION
SEL3.3_2.5# ( Pin 25 ) Input Level 1 0 CPU Operate at VDDLCPU = 2.5V VDDLCPU = 3.3V
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY 8. FUNCTION DESCRIPTION
8.1 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194R-630A initializes with default register settings, and then it ptional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller :
Clock Address A(6:0) & R/W
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2... until Stop
Set R/W to 1 when read back the data sequence is as follows, [1101 0011] :
Clock Address A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4... until Stop
8.2 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY
Frequency table by I2C
SSEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.8 100.2 83.3 133.6 75 100.2 100.2 133.6 66.8 97 97 95.2 140 112 96.2 166 SDRAM (MHz) 100.2 100.2 124.9 100.2 75 133.6 150.3 133.6 66.8 97 129.3 95.2 140 112 96.2 166 PCI (MHz) 33.4 33.4 33.2 33.4 37.5 33.4 33.4 33.4 33.4 32.3 32.3 31.7 35 37.3 32.1 33.3 REF (MHz) IOAPIC 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
8.2.1 Register 0: CPU Frequency Select Register (default = 0)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 0 = 0.5% Center type Spread Spectrum Modulation 1 = 0.75% Center type Spread Spectrum Modulation SSEL2 (for frequency table selection by software via I2C) SSEL1 (for frequency table selection by software via I2C) SSEL0 (for frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit 2, 6:4 SSEL3 (for frequency table selection by software via I2C) 0 = Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs Publication Release Date: Nov. 1999 Revision 0.65
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W83194R-630A
PRELIMINARY 8.2.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp x 1 1 1 1 1 1 1 Pin 43 45 46 Description Latched FS2# Reserved 0 = 0.5% down type spread, overrides Byte0-bit7. 1= Center type spread. Reserved CPUCLK2 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK0 (Active / Inactive) Reserved
8.2.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 14 13 12 11 9 8 7 Description Reserved PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive)
8.2.4 Register 3: Control Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 x 1 1 1 1 1 1 Pin 26 25 48 2 Description 1 Pin25 24_48MHz = 24MHz 0 Pin25 24_48MHz = 48MHz Latched FS0# 48MHz (Active / Inactive) 24-48MHz (Active / Inactive) Reserved Reserved REF1 (Active / Inactive) REF0X2 (Active / Inactive)
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY
8.2.5 Register 4: SDRAM Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 x 1 x 1 Pin 41 40 38 37 X 35 X 34 Description SDRAM13 (Active / Inactive) SDRAM12 (Active / Inactive) SDRAM11 (Active / Inactive) SDRAM10 (Active / Inactive) Latched FS1# SDRAM9 (Active / Inactive) Latched FS3# SDRAM8 (Active / Inactive)
8.2.6 Register 5: SDRAM Register(1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 32 31 29 28 21 20 18 17 SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) Description
8.2.7 Register 6: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 1 1 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY
9. ORDERING INFORMATION
Part Number W83194R-630A Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
10. HOW TO READ THE TOP MARKING
W83194R-630A 28051234 942GED
1st line: Winbond logo and the type number: W83194R-630A 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 942 G E D 942: packages made in '99, week 42 G: assembly house ID; O means OSE, G means GR E: Internal use code D: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Nov. 1999 Revision 0.65
W83194R-630A
PRELIMINARY 11. PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
Publication Release Date: Nov. 1999 Revision 0.65
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